Many electronic circuits and systems include the need for protection against inrush current, a short duration current surge due to a highly capacitive initial power load. Inrush current is particularly a problem within telecommunications systems which typically provide distributed 48 volts battery to all of the circuits throughout the network.
Telecommunications circuits are usually formed as small plug-in circuit boards carrying and interconnecting solid state and passive circuit elements. Such circuit elements typically require voltages lower than the nominal 48 volt common battery, and so DC to DC power conversion modules are typically included on each such plug-in board to provide suitable lower operating DC voltages, such as 5 volts and 12 volts. One characteristic of the DC to DC power conversion modules is that it presents a highly capacitive initial power load to the supply bus, with resultant enormous instantaneous current flow when power is first applied.
When such a circuit board is plugged in to a voltage source the inrush current is extremely high. In order to protect connectors, fuses and the circuit components from damage, the inrush current must be limited to an acceptable level. Furthermore, particularly within telecommunications systems where the availability of continuous service for the service subscriber is mandatory, modules are plugged into and out of the system without shutting down the 48 volt common battery. Intermittent contact of power pins on insertion and removal of circuit boards requires that any inrush current limiting circuit respond very quickly.
In U.S. Pat. No. 5,010,293, issued on Apr. 23, 1991 to Ellersick, an inrush current limiting circuit is described. The circuit of Ellersick uses an FET in series with a conduction path from the power source to load. The voltage across a current sensing resistor which is also in the conduction path is monitored by a bipolar transistor. The transistor generates an output in proportion to the current through the sensing resistor and controls the operation of the FET to limit the inrush current. In U.S. Pat. Nos. 5,087,871, issued on Feb. 11, 1992 to Losel, and 4,631,470, issued on Dec. 23, 1986 to Bingley, inrush current limiting circuits include a surge limiting resistor in parallel with an FET. During the power up, the surge limiting resistor limits the inrush current and in the steady state operation the FET is conducting to shunt the surge limiting resistor. A time delay circuit is made up of resistors and capacitors and has a large time constant. The time delay circuit controls the potential of the FET gate so that the FET turns on more slowly than the inrush current. The current limiting in Losel and Bingley is a passive action by a surge current limiting resistor, that is to say, the action is linear and not dynamic, so that the current is limited in proportion to the voltage instead of in proportion to the rate of change in voltage. Their circuits also contain a large time constant which may be longer than the momentary power interruption. The circuits are not fast acting and thus will not limit the current when the power is disrupted for a very short period of time. The circuit of Ellersick, on the other hand, appears quick acting due to the lack of capacitive components. However, it contains a current sensing resistor in series with a conduction path. The resistor is always in the conduction path and dissipates a rather large amount of power all the time.